1. Field of the Invention
The present invention relates to a semiconductor apparatus and more particularly, to a semiconductor apparatus provided with a semiconductor resistance area using impurity diffusion layers.
2. Related Art of the Invention
In recent years, a high voltage-withstanding semiconductor apparatus has been mounted in the output circuit of a microcomputer for directly driving a fluorescent display tubes. During the promotion of the higher performance of the semiconductor integrated circuit, further precision is demanded for a semiconductor apparatus provided with a resistance area in the high voltage-withstanding semiconductor apparatus to be used in the output circuit.
The conventional semiconductor apparatus will be described hereinafter with reference to the drawings.
FIG. 6 (A) is a plan view showing the essential portions of the conventional semiconductor apparatus. FIG. 6 (B) is a sectional view taken along a line A-B of FIG. 6 (A) (for example: Japanese Application Laid-Open No. Hei 6-45601).
In the semiconductor apparatus, an impurity diffusion layer 2 provided on the surface of the N-type semiconductor substrate 1 of a face bearing (100) is a P-type impurity diffusion layer which becomes a mother body of a resistor. The semiconductor substrate 1 is made of silicon. The PN function between the semiconductor substrate 1 and the impurity diffusion layer 2 on the surface of the semiconductor substrate 1 is positioned beneath the field oxide film 3. Thus, the function between the semiconductor substrate 1 and the impurity diffusion layer 2 can withstand the voltage of approximately +60V, so as to realize the higher pressure withstanding operation.
The active area 4 is not covered with a field oxide film 3 on the impurity diffusion layer 2. The P-type impurity diffusion layer 5 with the impurity concentration being approximately middle is provided in the area 4. The impurity diffusion layer 5 is formed so that the impurity concentration thereof may made higher than that on the surface of the impurity diffusion layer 2, and the diffusion depth thereof may be shallower than that of the impurity diffusion layer 2. The impurity diffusion layers 2 and 5 are respectively made optimal in impurity concentration for desired resistance value and pressure withstanding.
The impurity diffusion layers 6 and 7 are provided respectively for electric ohmic contact among aluminum electrodes 9, 10, and an impurity diffusion layer (including an impurity diffusion layer 2). The aluminum electrodes 9 and 10 are respectively connected with impurity diffusion impurity diffusion layers 6 and 7 through holes provided in a layer insulating film 8.
Two resistors composed of each of the impurity diffusion layer 2 and 5 can be connected in parallel in the semiconductor apparatus (hereinafter referred to as a semiconductor resistance apparatus) constructed as described above. The dispersion of the resistance values can be made smaller than that of the resistances value when the impurity diffusion layer 2 or the impurity diffusion layer 5 is formed singly. The dispersion of the resistance values can be restrained even if the resistance values of the impurity diffusion layer 2 are dispersed, because the concentration of the impurity diffusion layer 2 where the dispersion of the resistance values is originally less in terms of the manufacturing step is set higher than that of the diffusion diffusion layer 2. Therefore, an apparatus can be realized where the dispersion of the resistance values is smaller as a whole. Reasons why the resistance values of the impurity diffusion layer 5 are hard to disperse originally in terms of relationship of the manufacturing step are as follows.
Namely, the other successive steps which can give changes to the resistance values are reduced in the case of the impurity diffusion layer 5. In the case of the impurity diffusion layer 2, there are many factors which can change the initial resistance values, because many other steps such as thermal treating steps or the like are available after the impurity diffusion layer 2 has been formed.
The input output circuit using the semiconductor resistance apparatus constructed as in FIG. 6 (A) through FIG. 6 (B) will be described with the use of FIG. 7.
The source of the P channel transistor 100 is connected with a Vdd power source (+5V) and the drain is connected with the output terminal 102 and one end of the semiconductor resistance apparatus 101. The other end of the semiconductor resistance apparatus 101 is connected with the Vpp power source (-30V). The fluorescent display tube is connected with the output terminal 102. The florescent display tube can be equivalently regarded as capacity 104.
In the conductive condition of the P channel transistor 100, the electric potential of the output terminal 102 rises up to an approximate power voltage Vdd. In the non-conductive condition, it drops down to the power voltage Vpp.
The semiconductor resistance apparatus 101 corresponds to the conventional semiconductor apparatus in FIG. 6 (A) through FIG. 6 (B). The impurity diffusion layer 6 shown in FIG. 6 is connected with the output terminal 102, the impurity diffusion layer 7 is connected with the Vpp power source (-30V), and the N-type silicon substrate 1 is connected with the Vdd power source (+5V). Thus, the semiconductor resistance apparatus 101 functions as the high resistance of an inverter for outputting the high voltage.
However, the conventional semiconductor apparatus had a problem in that the resistance value was sometimes varied largely as time passed by long hours' use, and especially under higher temperatures. Or causes made by such time dependent changes were not explained.